Peak current control is a popular control technique in switched mode power supply (SMPS) topologies such as buck, boost and buck-boost power converters and their derived topologies for improved dynamic response, greater noise rejection, flux balancing in magnetic components, cycle by cycle current limiting, and simplified load sharing between parallel connected SMPS equipment. A peak current controlled SMPS system typically has a compensator that generates a peak current reference signal. This signal is compared with a preprocessed inductor/switch current using a high speed analog comparator. The high speed analog comparator effectively controls a pulse width modulator (PWM) for the SMPS. When the preprocessed inductor/switch current exceeds the peak current reference signal (generated by the outer voltage compensator) the SMPS switch(es) is turned off. The SMPS power switch is turned on again after a programmed PWM switching period is completed, as a result of which a fixed frequency operation is achieved. The preprocessed inductor/switch current is nothing but the sensed inductor/switch current modified by a “slope compensation” ramp signal that modulates a downward slope onto the current reference value to stabilize the power circuit. The slope compensation ramp signal is necessary to implement the peak current control technique in SMPS topologies, since it eliminates sub-harmonic oscillations when the SMPS is operated at a PWM duty cycle of greater than fifty percent.
Digital Voltage Compensator with Analog Slope Compensation
Peak current control is typically an analog technique, implemented using linear amplifiers, e.g., analog operational amplifiers, digital flip-flops and analog comparators or by using dedicated Application Specific Integrated Circuits (ASICs). A popular method to implement the peak current control technique using a microcontroller involves replacing analog compensator with a digital compensator, thereby producing a “digital peak current reference signal.” This digital peak current reference signal is coupled to an input of a digital-to-analog converter (DAC). The output of the DAC is an (negative) input to a built in high speed analog comparator. The preprocessed inductor/switch current (using external circuitry) is typically provided to the positive terminal of the built in high speed analog comparator. It is to be noted that the implementation of slope compensation using the external analog network circuitry poses reliability issues due to additional component requirements.
An alternative to the above method could be to continuously subtract a digital ramp signal from the digital peak current reference signal provided by the digital compensator. This would require very high speed interrupts to digital processor that may be several times the switching frequency of the converter. Such a requirement restricts the PWM switching frequency range and thus renders this method less feasible for commercial SMPS that typically run at high switching frequency, especially using low cost microcontrollers.
Yet another alternative could be to provide a dedicated core or peripheral inside the microcontroller that specifically performs this math operation without central processing unit (CPU) intervention. However this added peripheral function would increase microcontroller cost.
Digital Voltage Compensator with Digital Slope Compensation
To implement a digital peak current control solution comprising a digital compensator and digital slope compensation in combination with an analog comparator, a few methods have been proposed in literature and some have been patented. One of the patented methods involves cycle-by-cycle measurements of input and output voltages for computing a slope compensation factor (Ksc). A mathematical expression, which is a function of Ksc, measured inductor/switch current and the digital peak current reference are used in determining the digital slope compensated peak current reference. The digital slope compensated peak current reference is loaded into a high speed DAC and the analog output thereof is applied to an input of a high speed analog comparator. This mathematical expression may require two division instructions and two multiplication instructions along with a few addition and subtraction instructions, which is computationally intensive and requires a powerful digital processor to properly execute in the short time between PWM cycles. This all digital compensation method is more fully described in U.S. Pat. No. 8,278,899 B2, issued Oct. 2, 2012; entitled “Digital Slope Compensation for Current Mode Control,” by Frank Schafmeister and Tobias Grote.